// Copyright (C) 1953-2022 NUDT
// Verilog module name - time_window_check
// Version: V4.0.0.20220916
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module time_window_check
(
        i_clk                      ,        
        i_rst_n                    ,
                        
        iv_desp                    ,
        i_desp_wr                  ,
                                                         
        iv_time_slot               ,                    
                            
        o_descriptor_wr            ,
        ov_outportbm               ,
        ov_priority                ,
        ov_bufid                   ,
        ov_flowid                  ,
        ov_inport                  ,
        o_discard                  ,

        ov_receive_slot_error_cnt          
);

// I/O
// clk & rst
input                       i_clk;
input                       i_rst_n;  
//from trl
input           [87:0]      iv_desp                  ;         
input                       i_desp_wr                ;         
//from ist                                         
input           [9:0]       iv_time_slot             ;
//output next module                
output reg                  o_descriptor_wr          ;
output reg      [32:0]      ov_outportbm             ;
output reg      [2:0]       ov_priority              ;
output reg      [8:0]       ov_bufid                 ;
output reg      [5:0]       ov_inport                ;
output reg      [13:0]      ov_flowid                ;
output reg                  o_discard                ;

output reg     [15:0]       ov_receive_slot_error_cnt;
//***************************************************
//   schedule descriptor of time-sensitive packet
//***************************************************
// internal reg&wire for state machine
always @(posedge i_clk or negedge i_rst_n) begin
    if(!i_rst_n) begin        
        o_descriptor_wr        <= 1'b0;
        ov_outportbm           <= 33'b0;
        ov_priority            <= 3'b0;
        ov_bufid               <= 9'b0;
        ov_flowid              <= 14'b0;
        ov_inport              <= 6'b0;
        o_discard              <= 1'b0;
        
        ov_receive_slot_error_cnt <= 16'b0;
    end
    else begin
        if(i_desp_wr)begin
            if(iv_desp[2:0] >= 3'd5)begin //st                      
                if(iv_desp[53:44] == iv_time_slot)begin//InjectSlot                                       
                    o_descriptor_wr        <= 1'b1;
                    ov_outportbm           <= iv_desp[86:54];
                    ov_priority            <= iv_desp[2:0];
                    ov_bufid               <= iv_desp[36:28];
                    ov_flowid              <= iv_desp[16:3];
                    ov_inport              <= iv_desp[42:37];                          
                    o_discard              <= iv_desp[87];                                        
                end
                else begin
                    o_descriptor_wr        <= 1'b1;
                    ov_outportbm           <= iv_desp[86:54];
                    ov_priority            <= iv_desp[2:0];
                    ov_bufid               <= iv_desp[36:28];
                    ov_flowid              <= iv_desp[16:3];
                    ov_inport              <= iv_desp[42:37];
                    o_discard              <= 1'b1;
                    ov_receive_slot_error_cnt <= ov_receive_slot_error_cnt + 1'b1;
                end                                    
            end
                   
            else begin//not st                       
                o_descriptor_wr        <= 1'b1;
                ov_outportbm           <= iv_desp[86:54];
                ov_priority            <= iv_desp[2:0];
                ov_bufid               <= iv_desp[36:28];
                ov_flowid              <= iv_desp[16:3];
                ov_inport              <= iv_desp[42:37];
                o_discard              <= iv_desp[87];                        
           end
        end
        else begin//i_desp_wr is low
            o_descriptor_wr         <= 1'b0;
            ov_outportbm            <= 33'b0;
            ov_priority             <= 3'b0;
            ov_bufid                <= 9'b0;
            ov_flowid               <= 14'b0;
            ov_inport               <= 6'b0;
            o_discard               <= 1'b0;                                
        end     
   end
end 
               
endmodule
